1. 512MB~2GB DDR 333 / 400 and DDR2 533/667/800 MHz
2. 168/184/240-pin socket type dual in line memory module (DIMM)
3. Data rate: 533/667/800Mbps (max.)
4. 2.5 V (SSTL-2 compatible) I/O for DDR products, 1.8V power supply for DDR2 products
5. Chipset organization: 64*8, 128*4, 128*8
2. 168/184/240-pin socket type dual in line memory module (DIMM)
3. Data rate: 533/667/800Mbps (max.)
4. 2.5 V (SSTL-2 compatible) I/O for DDR products, 1.8V power supply for DDR2 products
5. Chipset organization: 64*8, 128*4, 128*8
6. Double-data-rate architecture, two data transfers per clock cycle
7. Bi-directional, differential data strobe (DQS) is transmitted/received with data, to be used in capturing data at the receiver
8. Data inputs and outputs are synchronized with DQS
9. DQS is edge aligned with data for read, center aligned with data for write
10. Different clock inputs(CK and CK)
7. Bi-directional, differential data strobe (DQS) is transmitted/received with data, to be used in capturing data at the receiver
8. Data inputs and outputs are synchronized with DQS
9. DQS is edge aligned with data for read, center aligned with data for write
10. Different clock inputs(CK and CK)
11. DLL aligns DQ and DQS thansitions with CK transitions
12. Brands of chipset: ELPIDA, Mosel, NANYA,
13. Four internal banks for concurrent operation (component)
14. Posted CAS by programmable additive latency for better command and data bus efficiency
15. Programmable burst length: 2, 4, 8
16. Programmable/CAS latency (CL): 3
17. Refresh cycles: (8192 refresh cycles/64ms)
18. 2 variations of refresh: Auto refresh and self refresh
19. 7.8US maximum average periodic refresh interval
14. Posted CAS by programmable additive latency for better command and data bus efficiency
15. Programmable burst length: 2, 4, 8
16. Programmable/CAS latency (CL): 3
17. Refresh cycles: (8192 refresh cycles/64ms)
18. 2 variations of refresh: Auto refresh and self refresh
19. 7.8US maximum average periodic refresh interval
